Chip-on-wafer-on-substrate (CoWoS) refers to the advanced packaging technology that offers the advantage of a larger package size and more I/O connections. It allows 2.5D and 3D stacking of components to enable homogenous and heterogenous integration.

The CoWoS ® -S (Chip on Wafer on Substrate with silicon interposer) platform provides best-in-class package technology for ultra-high performance computing applications, such as artificial intelligence (AI) and super-computing.

Aug 8, 2024 · What is CoWoS-S? CoWoS-S uses a single silicon interposer and through-silicon vias (TSVs) to achieve high-speed electrical signal transmission between the chip and the substrate. However, single silicon interposers often face yield issues.

CoWoS -S Technology Silicon interposer 2.5D system integration for advanced SoC and HBM. One decade of production with high yield and premium quality

Oct 1, 2024 · We can see CoWoS-S shows a significant decrease from 68% in 2024 to 30% in 2026. CoWoS-L experiences strong growth, rising from 24% in 2024 to 65% in 2026. CoWoS-R remains relatively low and declines slightly over time, from 8% in 2024 to 5% in 2026.

In this paper, we introduce CoWoS-L, a new architecture in the CoWoS family, to address the large Si interposer defect-driven yield loss concern.

May 30, 2023 · The stable reliability results and excellent electrical performance indicate that the CoWoS-L architecture will continue the scaling momentum of CoWoS-S to meet the demand of future 2.5D SiP systems for HPC and AI deep learning.

Jan 20, 2025 · Figure 1 CoWoS-L marks a significant advancement over CoWoS-S in terms of performance and efficiency for AI and HPC applications. Source: TSMC. Huang also told Taiwanese reporters that Nvidia is still producing Blackwell’s predecessor, Hopper, using TSMC’s CoWoS-S advanced packaging technology. “It’s not about reducing capacity.

Jun 1, 2021 · Chip-on-Wafer-on-Substrate with Si interposer (CoWoS-S) is a TSV-based multi-chip integration technology that is widely used in high performance computing (HPC) and artificial intelligence (AI) accelerator area due to its flexibility to accommodate multiple chips of SoC, chiplet, and 3D stacks such as high bandwidth memory (HBM).

CoWoS® platform provides best-in-breed performance and highest integration density for high performance computing applications. This wafer level system integration platform offers wide range of interposer sizes, number of HBM cubes, and package sizes.